1. Field of the Invention
The present invention relates to plasma display panels, and more specifically to the testing of the output connections of a driver circuit for a plasma display panel.
2. Description of Related Art
A plasma display panel (PDP) is a matrix-type display having a matrix of cells arranged in rows (or lines) and columns. Each cell has a cavity filled with a rare gas, two drive electrodes, and deposit of red, green, or blue phosphor. A given cell of the display is lit by applying a high voltage between its drive electrodes. The high voltage causes the gas in the cavity to ionize and emit ultraviolet light, and the light excites the deposited phosphor to cause it to generate a luminous point of red, green, or blue light.
As shown in FIG. 1, each cell is connected at the intersection of a line and a column. More specifically, each cell Pij is connected by a first drive electrode to a conductor line Li that is common to all of the cells of the line bearing the sub-index i (where i is an integer between 1 and n) and by a second drive electrode to a conductor line Cj that is common to all of the cells of the column bearing the sub-index j (where j is an integer between 1 and m). Each of the conductor lines is externally connected a line electrode or a column electrode. To give an idea of size, a 50-inch screen in a 16/9 format typically has around 1000 line electrodes and 3000 column electrodes (i.e., n=1000 and m=3000). The line and column electrodes are also known as horizontal and vertical electrodes, respectively.
The driver circuits produce the high voltage drive signals that are required to set the cells of the panel to the lit or unlit state. A drive signal typically has a zero or negative potential (i.e., ground potential) in the low logic state, and a potential (with respect to ground) of around 100 to 150 volts in the high logic state. The logic states of the signals applied to the PDP line and column electrodes determine the cells that are driven to be lit and those that are driven to be unlit. At their input, the driver circuits receive low voltage control signals that typically have a zero potential in the low logic state and a potential (with respect to ground) of 5 volts in the high logic state.
As seen from the driver outputs, the plasma display panel electrodes can be regarded as a capacitor that must charged or discharged during an addressing sequence (i.e., when the high voltage drive signals change state) and a current source or sink whose current must be absorbed or supplied by the driver circuit during a sustain sequence (i.e., to maintain the lit or unlit states of the cells). Thus, the driver outputs for the PDP are designed to supply or absorb a current on the order of several tens of milliamps.
During operation, the lines are addressed sequentially (i.e., line by line). In particular, the line electrodes are selected one after the other by applying appropriate high voltage signals, and high voltage drive signals are also simultaneously applied to the column electrodes by the driver outputs. The potential differences generated between the drive electrodes of the cells determine their state (i.e., lit or unlit). This type of sequential addressing of the PDP electrode lines is possible by the virtue of the memory effect linked to the nature of the gas in the cell cavities.
FIG. 2 shows a plasma display panel 1 and the housing 3 of a driver module. The housing contains one or more printed circuits on which the one or more driver circuits (generally in integrated circuit form) are mounted. For example, an integrated circuit can contain 96 driver output stages. The outputs from the driver circuits are the outputs from those driver stages, and thus they can address 96 electrodes of the PDP. In other words, the output from each driver stage of the module drives a PDP column electrode. The 96 outputs from the integrated circuit are connected to their column electrodes through adapted connecting means (e.g., via conductive tracks etched on the printed circuit).
The plasma display panel 1 includes a glass plate 11 mounted on a substrate 12. The inner face of the plate 11 carries the phosphors (not shown), and the line electrodes and the column electrodes protrude from the glass plate 11 on the substrate 12. The electrical insulation between these different elements is provided by layers of dielectric material (not shown) and the inter-electrode pitch is very small (e.g., it can reach 100 microns). The driver module includes a housing 3, a low voltage control signal input connector (not shown), and the connecting means described above. The connecting means is typically a flat, flexible cable 5 having a set of parallel, mutually insulated conductors at a pitch equal to that of the column electrodes (i.e., 100 microns). In general, the flat cable 5 is a flexible printed circuit on which tracks are etched (a conductive track ribbon), and is stuck or pressed on the edge of the substrate 12 over the column electrodes Y.
During manufacturing, assembling the tracks of the flat cable 5 with the column electrodes Y is very critical. In particular, two types of faults can appear after the assembling operation: a bad contact between one track of the flat cable and at least one column electrode, which causes the cells of the corresponding column to not be driven; and a misalignment between the tracks of the flat cable and the column electrodes, which makes a track cause a short circuit between two adjacent column electrodes. According to manufacturers, the proportion of faults arising from non-connected or open circuit electrodes is 70% versus 30% of faults arising from a short circuit between two column electrodes.
The only conventional technique for testing the assembling of the connecting means involves powering up the plasma display panel and having it display a predetermined image. This allows a check of whether the displayed image corresponds to the expected image. A non-connected line and non-connected column electrode are respectively indicated on the screen by a horizontal or vertical line that remains dark. While this technique is reliable, it can only be implemented after the panel has been completely assembled. In particular, all of the panel's electronic circuits must be fitted, including those for generating the low voltage control signals and for the power supply. Thus, if there is a misalignment between the connecting means and the panel, it may be necessary to take the panel apart to correct the assembling fault.